List of selected publications

Year 2002

• A Case Study for the Verification of Complex Timed Circuits: IPCMOS.
  M.A. Peña, J. Cortadella, E. Pastor and A. Smirnov,
  Proc. of the Conf. on Design, Automation and Test in Europe (DATE).
  March 2002.

Year 2001

• A structural encoding technique for the synthesis of asynchronous circuits.
  J. Carmona, J. Cortadella and E. Pastor,
  2nd. Int. Conf. on Application of Concurrency to System Design (ICACSD),
  Newcastle upon Tyne (UK), June 2001, pp. 157-166.

• Symbolic Analysis of Bounded Petri Nets.
  E. Pastor, J. Cortadella and O. Roig.
  IEEE Transactions on Computers, Vol. 50, No. 5, May 2001, pp. 432-448.

Year 2000

• Formal verification of safety properties in timed circuits.
  M.A. Peña, J. Cortadella, A. Kondratyev and E. Pastor,
  Proc. Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems,
  Eliat (Israel), Apr. 2000, pp. 2-11.

Year 1999

• Structural Methods to Improve the Symbolic Analysis of Petri Nets.
  E. Pastor, J. Cortadella and M.A. Peña.
  Proc. 20th International Conference on Application and Theory of Petri Nets,
  Lecture Notes in Computer Science, vol. 1639, pp. 26-45, Springer Verlag, June 1999.

• Decomposition and Technology Mapping of Speed-Independent Circuits Using Boolean Relations.
  J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, E. Pastor and A. Yakovlev.
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 9, Sept. 1999, pp. 1221-1236.

Year 1998

• Efficient Encoding Schemes for Symbolic Analysis of Petri Nets.
  E. Pastor and J. Cortadella.
  Proc. of the Conference on Design, Automation and Test in Europe, 1998 (DATE'98), Paris, March 1998, pp. 790-795.
  The slides used in the conference are here in Powerpoint format.
  Slides used in conference at Newcastle University here in postscript format.
  

• Structural Methods Applied to the Symbolic Analysis of Petri Nets.
  E. Pastor and J. Cortadella.
  Proc. IEEE/ACM International Workshop on Logic Synthesis,
  June 1998.
  

• Hierarchical Communicating Nets for the Symbolic Analysis of Coordinated Systems.
  E. Pastor, A. Yakovlev and J. Cortadella.
  Special Interest Workshop on Exploitation of STG-based Design Technology,
  St. Petersburg, Russia, July 1998.
  Review the abstract here.
  

• Estimations of Power Consumption in Asynchronous Logic as Derived from Graph Based Circuit Representations.
  L. Lloyd, A. Yakovlev, E. Pastor and A. Koelmans.
  International Workshop - Power and Timing Modeling, Optimization and Simulation (PATMOS'98),
  October 1998.
  The slides used in the conference are here in Powerpoint format.
  Also in UK Low Power Forum, The University of Sheffield, September 1998.
  

• Structural Methods for the Synthesis of Speed-Independent Circuits.
  E. Pastor, J. Cortadella, A. Kondratyev and O. Roig.
  IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 17, No. 11, Nov. 1998, pp. 1108-1129.

Year 1997

• Partial Order Based Approach to Synthesis of Speed-independent Circuits.
  A. Semenov, A. Yakovlev, E. Pastor, M.A. Peña, J. Cortadella and L. Lavagno.
  Proc. 3nd Advanced Research in Asynchronous Circuits and Systems,
  April 1997, pages 254-265.
  

• Synthesis of Speed-independent Circuits from STG-unfolding Segment.
  A. Semenov, A. Yakovlev, E. Pastor, M.A. Peña and J. Cortadella.
  Proc. 34th Design Automation Conference,
  June 1997, pages 16-21.
  

• Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits.
  O. Roig, J. Cortadella, M.A. Peña and E. Pastor.
  Proc. 34th Design Automation Conference,
  June 1997, pages 620-625.
  

• Decomposition and Technology Mapping of Speed-Independent Circuits Using Boolean Relations.
  J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, E. Pastor and A. Yakovlev.
  Proc. International Conference on Computer-Aided Design,
  November 1997, pages 220-227.
  The slides used in the conference are here in Powerpoint format.
  

Year 1996

• Structural Methods for the Synthesis of Speed-Independent Circuits.
  E. Pastor, J. Cortadella, A. Kondratyev and O. Roig.
  Proc. European Design and Test Conference (EDAC-ETC-EuroASIC),
  March 1996, pages 340-347.
  The slides used in the conference are here in postscript format.
  

• Efficient Synthesis of Speed-independent Circuits from the STG Structure.
  E. Pastor, J. Cortadella, A. Kondratyev, and O. Roig.
  Proc. ACiD-WG Workshop,
  September 1996.
  

• Synthesis of Speed-independent Circuits from STG-unfolding Segment.
  A. Semenov, A. Yakovlev, E. Pastor, M.A. Peña and J. Cortadella.
  Proc. ACiD-WG Workshop,
  September 1996.
  

Year 1995

• Checking signal transition graph implementability by symbolic BDD traversal.
  A. Kondratyev, J. Cortadella, M. Kishinevsky, E. Pastor and O. Roig.
  Proc. European Design and Test Conference (EDAC-ETC-EuroASIC),
  March 1995, pages 325-332.
  

• A new look at the conditions for the synthesis of speed-independent circuits.
  E. Pastor, J. Cortadella and O. Roig.
  Proc. Fifth Great Lakes Symposium on VLSI (GLSVLSI'95),
  May 1995, pages 230-235.
  

• Hierarchical Gate-Level Verification of Speed-Independent Circuits.
  O. Roig, J. Cortadella and E. Pastor.
  Proc. 2nd Working Conference on Asynchronous Design Methodologies,
  May 1995, pages 128-137.
  

• Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets.
  O. Roig, J. Cortadella and E. Pastor.
  16th International Conference on Application and Theory of Petri Nets,
  June 1995, pages 374-391.
  

• Cover Approximations for the Synthesis of Speed-Independent Circuits.
  E. Pastor, J. Cortadella, A. Kondratyev, and O. Roig.
  Proc. IFIP TC10, WG 10.5 Workshop on Logic and Architecture Synthesis,
  December 1995, pages 150-159.
  The slides used in the conference are here in postscript format.

Year 1994

• Symbolic Model-Checking of Petri Nets for Speed-Independent Circuits.
  O. Roig, E. Pastor and J. Cortadella.
  Proc. ACiD-WG/EXACT Workshop on Asynchronous Low-Power VLSI,
  April 1994.
  

• Analysis of Petri Nets with Boolean Manipulation.
  E. Pastor, O. Roig, J. Cortadella and R.M. Badia.
  Proc. 15th International Conference on Application and Theory of Petri Nets,
  June 1994, pages 416-435.
  

• Verificacion de circuitos independientes de la velocidad con modelos simbolicos de redes de Petri.
  O. Roig, E. Pastor and J. Cortadella.
  Proc. IX Congreso de Diseño de Circuitos Integrados,
  November 1994, pages 307-312.

Year 1993

• An Efficient Unique State Coding Algorithm for Signal Transition Graphs.
  E. Pastor and J. Cortadella.
  Proc. IEEE International Conference on Computer Design (ICCD),
  October 1993, pages 174-177.
  

• Polynomial Algorithms for the Synthesis of Hazard-Free Circuits from Signal Transition Graphs.
  E. Pastor and J. Cortadella.
  Proc. IEEE International Conference on Computer-Aided Design (ICCAD),
  November 1993, pages 250-254.
  

• Sintesis de Maquinas de Control para Circuitos Asincronos.
  O. Roig, E. Pastor, J. Cortadella and R.M. Badia.
  Proc. VIII Congreso de Diseño de Circuitos Integrados,
  November 1993, pages 326-331.

Year 1992

• A High-Level Synthesis System for Asynchronous Circuits.
  J. Cortadella, R.M. Badia, E. Pastor and A. Pardo.
  Proc. Sixth International Workshop on High-Level Synthesis,
  November 1992, pages 87-94.