Register renaming and out-of-order instruction issue are now commonly
  used in superscalar processors.  These techniques can also be used
  to significant advantage in vector processors, as this paper shows.  
  Performance is improved and available memory bandwidth is used
  more effectively. Using a trace driven simulation for a vectorizable subset of
  the Perfect Club and Specfp92 programs we compare a conventional vector implementation, 
  based on the Convex C3400 with an out-of-order, register renaming, vector implementation.
  When the number of physical registers is above 12, out-of-order execution coupled with 
  register renaming provides a speedup of 1.24--1.72 for realistic memory latencies. With an 
  ideal memory system with no latency, there is still a speedup of as much as 
  1.15--1.25. When memory latencies are varied, using out-of-order techniques allows much 
  more latency tolerance than traditional vector implementations. Memory latencies of 100 
  cycles generally result in performance degradation less than 6\%.
  The mechanisms used for register renaming and out-of-order issue
  can also be used to support precise exceptions -- generally a difficult
  problem in vector machines.  When precise exceptions are implemented,
  there is typically less than a 10\% degradation in performance.
  A new technique based on register renaming is targeted at dynamically
  eliminating spill code; this technique
  is shown to provide an extra speedup ranging between 1.10 and 1.20
  while reducing total memory traffic by an average of 15--20\%.