1999

• Exploiting a New Level of DLP in multimedia applications, (Document not Available)

Jesus Corbal, Roger Espasa, Mateo Valero
In  Proceedings of the 32nd Annual International Symposium on Microarchitecture (MICRO-32), Haifa, Israel, December 1999
• MOM: a Matrix oriented Instruction Set Architecture for Multimedia Applications, (Document not Available)

Jesus Corbal, Roger Espasa, Mateo Valero
In SC'99 , Portland, Oregon, December 1999
• A Simulation Study of Decoupled Vector Architectures, (Compressed Postscript 262Kb) (Abstract)

Roger Espasa and Mateo Valero
Journal of Supercomputing,  October 1999, Kluwer Academic Publishers
• Adding a Vector Unit to a Superscalar Processor (Postscript 716Kb)

Francisca Quintana, Jesus Corbal, Roger Espasa and Mateo Valero
In International Conference on Supercomputing (ICS) , ACM Computer Society Press, Rhodes, Greece, June 1999.

• Command Vector Memory Systems: High Performance at Low Cost (Postscript 755Kb)

Jesus Corbal, Roger Espasa and Mateo Valero
In International Conference on Parallel Architectures and Compilations Techniques (PACT) , Paris, France, October 1998.
• A Performance Study of Out-of-Order Vector Architectures and Short Registers,

Luis Villa, Roger Espasa and Mateo Valero
In International Conference on Supercomputing (ICS) , ACM Computer Society Press, Melbourne, Australia, June 1998.
• Effective Usage of Vector Registers in Decoupled Vector Architectures

Luis Villa, Roger Espasa and Mateo Valero
In Euromicro Workshop on Parallel and Distributed Processing, IEEE Computer Society Press, January 1998
• A Case for Merging the ILP and DLP paradigms
  Francisca Quintana,  Roger Espasa and Mateo Valero
  In Euromicro Workshop on Parallel and Distributed Processing, IEEE Computer Society Press, January 1998

• Simultaneous Multithreaded Vector Architecture: Merging ILP and DLP for High Performance (Compressed Postscript 110Kb)(Abstract)

Roger Espasa, Mateo Valero and James E. Smith
In International Conference on High Performance Computing (HiPC),  Bangalore, India, December 1997,
• Out-of-order Vector Architectures, (Compressed Postscript 177Kb) (Abstract)

Roger Espasa, Mateo Valero and James E. Smith
In  Proceedings of the 30th Annual International Symposium on Microarchitecture (MICRO-30), Research Triangle Park, NC, December 1997
• Effective Usage of Vector Registers in Advanced Vector Architectures, (Compressed Postscript 207Kb) (Abstract)

Luis Villa, Roger Espasa and Mateo Valero
In Parallel Architectures and Compilation Techniques (PACT'97), San Francisco, CA, November 1997
• Exploiting Instruction- and Data- Level Parallelism, (Compressed Postscript 101Kb) (Abstract)

Roger Espasa and Mateo Valero
IEEE MICRO (Special Issue on Computing with a Billion Transistors), pg. 20-27, September/October 1997
• A Victim Cache for Vector Registers (Compressed Postscript 130Kb) (Abstract)

Roger Espasa and Mateo Valero
In International Conference on Supercomputing, ACM Computer Society Press, Vienna, Austria, July 1997.
• Multithreaded Vector Architectures, (Compressed Postscript 180Kb) (Abstract)

Roger Espasa and Mateo Valero
In Third Internationl Symposium on High-Performance Computer Architecture, IEEE Computer Society Press, pag. 237-249, San Antonio, TX, February 1997.
• On the Instruction Level Characterization of the Specfp92 programs on a vector computer, (Compressed Postscript 104Kb)(Abstract)

Roger Espasa and Mateo Valero
In Supercomputation in Nonlinear and Disordered Systems: Algorithms, Applications and Architectures , World Scientific Publishing, 1997.

• Decoupled Vector Architectures, (Compressed Postscript 146Kb) (Abstract)

Roger Espasa and Mateo Valero
In Second Internationl Symposium on High-Performance Computer Architecture, IEEE Computer Society Press, pag. 281-290, San Jose, CA, February 1996.

1995

• Instruction Level Characterization of the Perfect Club programs on a vector computer, (Compressed Postscript 114Kb)(Abstract)

Roger Espasa and Mateo Valero
In XV International Conference of the Chilean Computation Society, SCCC Press, pag. 198-209, January 1995.
• Quantitative Analysis of Vector Code (Compressed Postscript 65Kb) (Abstract)

Roger Espasa, Mateo Valero, David Padua, Marta Jiménez and Eduard Ayguade
In Euromicro Workshop on Parallel and Distributed Processing, IEEE Computer Society Press, San Remo, Italy, January 1995.