The goal of this paper is to show that instruction level parallelism (ILP) and  data-level
 parallelism (DLP) can be merged in a single simultaneous vector multithreaded architecture to
 execute regular vectorizable code at a performance level that can not be achieved using either
 paradigm on its own. We will show that the combination of the two techniques yields
 very high performance at a low cost and a low complexity: We will show that this architecture 
 achieves a sustained performance on numerical regular codes that is 20 times the performance 
 that can be achieved with
 today's superscalar microprocessors. Moreover, we will show that the architecture can tolerate
 very large memory latencies, of up to a 100 cycles, with a relatively small performance
 degradation. This high performance is independent of working set size or of locality
 considerations, since the DLP paradigm allows very efficient explotaition of a high performance
 flat memory bandwidth. The total transistor budget to implement such architecture is estimated to be
 under 60 million transistors, leaving plenty of room to add either cache or main memory on the same die.