myself

Jaume Abella Ferrer

Email: myemail
Co-director of the CAOS group (Embedded Systems group)
Barcelona Supercomputing Center (BSC)

c/ Jordi Girona, 31
Edifici Til.lers, 4th floor
Barcelona - Catalunya Spain
phone: +34 93 4137609
fax: +34 93 4137721
ORCID: 0000-0001-7951-4028
RISC-V SIG-safety vice-chair

OPEN PhD/Master POSITIONS at BSC in the area of Embedded Systems: Details here

CURRENT PROJECTS
My main interests are on the timing and functional verification of critical real-time systems, with particular emphasis on the automotive, avionics, space and railway domains, and with a clear constraint: applicability in industrial products (either in the short or long term).
My research is often articulated through collaborative projects with industry:
  • Microprocessor design for safety critical systems, see SMARTY (web TBD), ISOLDE, NimbleAI, NEUROPULS, FRACTAL, De-RISC, SELENE, EPI
  • Use of AI in safety critical systems, see CAPSUL-IA (web TBD), EdgeAI-Trust (web TBD), SAFEXPLAIN, REBECCA
  • Timing verification with MicroBenchmarks technology, see MASTECS
  • Timing verification for Space systems, together with the European Space Agency (ESA), see [ESA projects]
  • Timing verification with probabilistic means with Avionics, Space, Railway and Automotive industry, see SuPerCom, PROXIMA, PROARTIS
  • Timing verification on COTS processors, see SAFURE
  • Functional verification on automotive processors (Infineon), see VeTeSS
  • Timing verification on time-determistic processor prototypes, see parMERASA


    • PAST ACTIVITIES
    EDUCATION
    Current Ph.D. and Master students: Past Ph.D. students: Past Master students: Ph.D. and Master committees: