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Combining logic, memory, and a processor core, embedded
processor solutions allow engineers to integrate an entire system on a
single programmable logic device (PLD). As an example, Altera® offers
two families -the NiosTM soft core embedded processor and the ARM®-based
hard core embedded processor. Embedded processors give the flexibility
of processor cores with the integration of system-on-a-programmable-chip
(SOPC) logic.
Nios
Soft Processor
The Nios® CPU instruction set architecture is optimized for programmable
logic and system-on-a-programmable-chip (SOPC) integration. The Nios CPU
is a five-stage pipelined general-purpose RISC microprocessor that supports
both 32-bit and 16-bit architectural variants. Both the 32-bit and 16-bit
Nios CPUs utilize a 16-bit instruction format to reduce code footprint
and instruction memory bandwidth. The Nios instruction set is targeted
for compiled embedded applications.
Nios® embedded processor-based systems include one or more
Nios CPUs as well as Avalon™ peripherals and automatically-generated bus
matrix connections. The Nios embedded processor is optimized for Altera®
programmable logic and system-on-a-programmable chip (SOPC) integration.
This configurable, general-purpose RISC processor can be easily combined
with user logic and programmed into a PLD. The Nios CPU can be configured
for a wide range of applications. A 16-bit Nios CPU, running a small program
out of an on-chip ROM in an embedded system block (ESB), makes an effective
sequencer or controller and can take the place of a hard-coded state machine.
A 32-bit Nios CPU with external flash memory and a large external main
memory is a powerful 32-bit embedded processor system. Advanced features,
such as custom instructions and the simultaneous multi-master Avalon bus,
make the Nios embedded processor a powerful processing solution.
See an image of the Nios development
board.
ARM
Processor
The ARM®-based embedded processor programmable logic devices (PLDs) integrates
a high-performance hard processor core with a PLD programmable architecture.
The resulting device family provides designers cost-effective access to
advanced processor technologies. As an example, Altera offers the ARM922T™
RISC processor core embedded into a stripe on the PLD. The stripe contains
the processor with its associated caches and memory management units (MMUs),
dual-port and single-port SRAM memory, peripherals, and debugging modules.
The industry-standard AMBA™ high-performance bus (AHB) architecture allows
full operation speed through the stripe, and dedicated bus bridges and
dual-port SRAM provide interfaces to the logic portion of the devices.
The ARM processor core in Excalibur devices operates at speeds of up to
200 MHz, equivalent to 210 Dhrystone MIPS. The integrated SDRAM controller
supports single data rate (SDR) or double data rate (DDR) SDRAM at up
to 133 MHz or 266 MHz, respectively, and the device supports up to 512
Mbytes of SDRAM. In addition, the device offers an expansion bus interface
(compatible with industry-standard flash memory), SRAM and memory-mapped
peripherals. The expansion bus interface can support up to four external
devices, each up to 32 Mbytes. The stripe includes several standard peripherals,
including an interrupt controller, a UART, and a general-purpose timer.
A watchdog timer in the stripe provides system checks, and an embedded
trace module assists in software debugging. Furthermore, an ETM9 module
within the stripe allows real-time capture of events when used in conjunction
with third-party trace modules.
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