Research activities

During my sabattical at Harvard University, I had the chance to work together with Professors David Brooks and Gu-Yeon Wei. Together we started working on variation-aware architectures. In detail, we are studying the advantages of using dynamic memories for on-chip structures. Back at UPC, part of this research evolved into the TRAMS and CLERECO projects. This work continues through a collaboration with BSC in the system-level analysis and countermeasures within the RECIPE project first, and the FRACTAL project currently.

Papers in: Conferences     Journals     Posters

Papers (Conferences)

• "SafeX: Open Source Hardware and Software Components for Safety-Critical Systems"
  S. Alcaide, G. Cabo, F. Bas, P. Benedicte, F. Fuentes, F. Chang, I. Lasfar, R. Canal, J. Abella
  2022 IEEE Forum on specification and Design Languages Sept. 2022.

• "SafeDX: Standalone Modules Providing Diverse Redundancy for Safety-Critical Applications "
  R. Canal, F. Bas, S. Alcaide, G. Cabo, P. Benedicte, F. Fuentes, F. Chang, I. Lasfar, J. Abella
  2022 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) July 2022.

• "SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays "
  R. Canal, Y. Sazeides, A. Bramnik,
  2021 IEEE Design, Automation and Test in Europe Conference (DATE) February 2021.

• "2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD)"
  Y. Sazeides, A. Bramnik, R. Gabor, C. Nicopoulos, R. Canal, D. Konstantinou, G. Dimitrakopoulos
  2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) October 2020.

• "Challenges in Deeply Heterogeneous High Performance Systems"
  G.Agosta, W. Fornaciari, A. Cilardo, J.Flich, C. Hernandez, M. Kulczewski, G. Massari, R. Tornero, M. Zapater, D. Atienza and R. Canal
  2019 EUROMICRO Digital System Design Conference, Kallithea (Greece), August 2019.

• "Modern Gain-Cell Memories in Advanced Technologies"
  E. Amat, R. Canal, A. Rubio
  24th IEEE International On-Line Testing Symposium (IOLTS'18), Platja d'Aro (Catalonia), July 2018

• "Review on new eDRAM configurations for next nano-metric electronics era"
  E. Amat, A. Calomarde, R. Canal, A. Rubio
  8th International Conference on Materials Engineering for Resources (ICMR2017),  Akita (Japan), October 2017

• "Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level"
  E. Amat, A. Calomarde, R. Canal, A. Rubio
  27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS),  Thessaloniki (Greece), September 2017

• "MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment"
  M. Kaliorakis, D. Gizopoulos, R. Canal, A. Gonzalez
  IEEE/ACM International Symposium on Computer Architecture (ISCA-44),  Toronto (Canada), June 2017

• "Cross-Layer System Reliability Assessment Against Hardware Faults"
  A. Vallero, A. Savino, G. Politano, S. Di Carlo, A. Chatzidimitriou, S. Tselonis, M. Kaliorakis, D. Gizopoulos, M. Riera, R. Canal, A. Gonzalez, M. Kooli, A. Bosio, G. Di Natale
  IEEE International Test Conference (ITC-47),  Fort Worth (TX, USA), November 2016

• "SRAM Memory Margin Probability Failure Estimation using Gaussian Process Regression "
  M. Rana, R. Canal, J. Han and B. Cockburn
  IEEE International Conference on Computer Design   (ICCD-34),  Phoenix (AZ, USA), October 2016

• "MASkIt: Soft Error Rate Estimation for Combinational Circuits"
  M. Anglada, R. Canal, J. L. Aragón and A. González
  IEEE International Conference on Computer Design   (ICCD-34),  Phoenix (AZ, USA), October 2016

• "Statistical Analysis and Comparison of 2T and 3T1D e-DRAM Minimum Energy Operation"
  M.Rana, R.Canal, E.Amat, A.Rubio
  22th IEEE International On-Line Testing Symposium (IOLTS'16), St. Feliu de Guíxols (Catalonia), July 2016

• "A Detailed Methodology to Compute Soft-Error Rates in Advanced Technologies"
  M. Riera, R. Canal, J. Abella. A. Gonzalez
  IEEE Design, Automation and Test in Europe Conference (DATE’16),  Dresden (Germany), March 2016

• "Early Component-Based System Reliability Analysis for Approximate Computing Systems"
  A. Vallero, A. Savino, G. Michele, M. Politano, S. Di Carlo, A. Chatzidimitriou, S. Tselonis, M. Kaliorakis, D. Gizopoulos, M. Riera, R. Canal, A. Gonzalez, M. Kooli, A. Bosio and G. Di Natale.
  2nd Workshop on Approximate Computing (WAPCO) (together with Hipeac Conference), Prague (Czech Republic), January 2016

• "Variability - Aware Design Space Exploration Of Embedded Memories"
  S. Ganapathy, G. Karakonstantis, A. Burg and R. Canal
  IEEE 28th Convention of Electrical and Electronics Engineers in Israel, Eilat (Israel), December 2014

• "REEM: Failure/Non-Failure region Estimation  method for SRAM yield analysis"
  M. Rana, R. Canal
  IEEE International Conference on Computer Design   (ICCD-32),  Seoul (Korea), October 2014

• "iRMW: A Low-Cost Technique to Reduce NBTI-Dependent Parametric Failures in L1 Caches"  (Best paper nomenee)
  S. Ganapathy, R. Canal, A. Gonzalez, A. Rubio 
  IEEE International Conference on Computer Design   (ICCD-32),  Seoul (Korea), October 2014

• "Variability impact on on-chip memory data paths"
  E. Amat, A. Calomarde, R. Canal, A. Rubio
  IEEE 5th European Workshop on CMOS Variability (VARI'14),  Palma de Mallorca (Spain), September-October 2014

• "Cross-layer early reliability evaluation: Challenges and promises" (invited paper)
  S. Di Carlo, A. Vallero, D. Gizopoulos, G. Di Natale, A. Gonzalez, R. Canal, R. Mariani, M. Pipponzi, A. Grasset, P. Bonnot, F. Reichenbach, G. Rafiq, T. Loekstad
  20th IEEE International On-Line Testing Symposium (IOLTS'14), Platja d'Aro (Catalonia), July 2014

• "SSFB: A Highly-Efficient and Scalable Simulation Reduction Technique for SRAM Yield Analysis"
  M. Rana, R. Canal
  IEEE Design, Automation and Test in Europe Conference (DATE’14),  Dresden (Germany), March 2014

• "DRAM-based Coherent Caches and how to take advantage of the coherence protocol to reduce the refresh power"
  Z. Jakšić, R. Canal
  IEEE Design, Automation and Test in Europe Conference (DATE’14),  Dresden (Germany), March 2014

• "INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis
  S. Ganapathy, R. Canal, D. Alexandrescu, E. Costenaro, A. Gonzalez and A. Rubio
  IEEE Design, Automation and Test in Europe Conference (DATE’14),  Dresden (Germany), March 2014

• "FinFET and III-V/Ge technology impact on 3T1D cell behavior"  (slides)
  E. Amat, A. Calomarde, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio
  Intel Ireland Research Conference (IIRC), Dublin (Ireland), November 2013.

• "Variability Robustness Enhancement for 7nm FinFET 3T1D-DRAM Cells "
  E. Amat, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio
  IEEE 55th International Midwest Symposium on Circuits and systems (MWSCAS 2013) Columbus (Ohio, USA), August 2013

• "An Energy-Efficient and Scalable eDRAM-Based Register File Architecture for GPGPU"
  N. Jing, Y. Shen, Y. Lu, S. Ganapathy, Z. Mao, M. Guo, R. Canal, X. Liang
  ACM/IEEE 40th International Conference on Computer Architecture (ISCA'13), Tel-Aviv (Israel), June 2013

• "Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes"
  V. Lorente, A. Valero, J. Sahuquillo, S. Petit, R. Canal, P. Lopez, J. Duato
  IEEE Design, Automation and Test in Europe Conference (DATE’13),  Grenoble (France), March 2013

• "On the Effectiveness of Hybrid Recovery Techniques on Parametric Failures"
  S. Ganapathy, R. Canal,  A. Gonzalez, A. Rubio
  30th IEEE International Symposium on Quality Electronic Design (ISQED'13), Santa Clara (California, USA), March 2013

• "Effects of FinFET Technology Scaling on 3T and 3T1D Cell Performance Under Process and Environmental Variations"
  Z. Jakšić, R. Canal
  3rd Workshop on Workshop on Resilient Architectures, in conjunction with the 45th Annual IEEE/ACM International Symposium on Microarchitecture, Vancouver (Canada), December 2012

• "Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm" (Best Paper Award)
  E. Amat, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio
  27th Conference on Design of Circuits and Integrated Systems (DCIS 2012), Avignon (France), November 2012

• "Impact of Bulk/SOI 10nm FinFETs on 3T1D-DRAM cell performance "
  E. Amat, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio
  11th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2012), Xian (China), October 2012

• "Enhancing 3T DRAMs for SRAM replacement under 10nm Tri-Gate SOI FinFETs"
  Z. Jakšić, R. Canal
  30th IEEE International Conference on Computer Design (ICCD'12), Montreal (Quebec), September 2012

• "A Novel Variation-Tolerant 4T-DRAM with Enhanced Soft-Error Tolerance"
  S. Ganapathy, R. Canal, D. Alexandrescu, E. Costenaro, A. Gonzalez, A. Rubio
  30th IEEE International Conference on Computer Design (ICCD'12), Montreal (Quebec), September 2012

• "Analysis of FinFET Technology on Memories" (invited paper)
  E. Amat, A. Asenov, R. Canal, B. Cheng, J-L. Cruz, Z. Jakšić, M. Miranda, A. Rubio, P. Zuber
  18th IEEE International On-Line Testing Symposium (IOLTS'12), Sitges (Catalonia), June 2012

• "Enhancing 6T SRAM Cell Stability by Back Gate Biasing Techniques for 10nm SOI FinFETs under Process and Environmental Variations"
  Z. Jakšić, R. Canal
  19th International Conference on  Mixed Design of Integrated Circuits and Systems, Warsaw (Poland), May 2012

• "Strain Relevance on the Improvement of the 3T1D Cell Performance"
  E. Amat, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio
  19th International Conference on Mixed Design of Integrated Circuits and Systems, Warsaw (Poland), May 2012

• "Dynamic Fine-Grain Body Biasing of Caches with Latency and Leakage 3T1D-Based Monitors"
  S. Ganapathy, R. Canal, A. Gonzalez, A. Rubio
  29th IEEE International Conference on Computer Design (ICCD'11), Amherst (MA, USA), October 2011

• " New reliability mechanisms in memory design for sub-22nm technologies" (invited paper)
  N. Aymerich, A. Asenov, A. Brown, R. Canal, B. Cheng, J. Figueras, A. Gonzalez, E. Herrero, S. Markov, M. Miranda, P. Pouyan, T. Ramirez, A. Rubio, I. Vatajelu, X. Vera, X. Wang, P. Zuber
  17th IEEE International On-Line Testing Symposium (IOLTS'11), Athens (Greece), July 2011

• "Impact of Positive Bias Temperature Instability (PBTI) on 3T1D-DRAM Cells"
  N. Aymerich, S. Ganapathy, A.Rubio, R. Canal, A. Gonzalez
  IEEE/ACM Great Lakes Symposium on VLSI, Lausanne (Switzerland), May 2011

• "MODEST : A Model for Energy Estimation under Spatio-Temporal Variability"
  S. Ganapathy, R. Canal, A. Gonzalez, A. Rubio
  15th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2010) , August 2010 (Austin, Texas)

• "Circuit Propagation Delay Estimation Through Multivariate Regression-Based Modeling Under Spatio-Temporal Variability"
  S. Ganapathy, R. Canal, A. Gonzalez, A. Rubio
  IEEE Design, Automation and Test in Europe Conference (DATE’10), March 2010 (Dresden, Germany)

• "An hybrid eDRAM/SRAM macrocell to implement first-level data caches "
  A. Valero, J. Sahuquillo, S. Petit, V. Lorente, R. Canal, P. Lopez, J. Duato
  IEEE/ACM International Symposium on Microarchitecture (MICRO-42), December 2009 (New York, New Jersey)

• "Process Variation Tolerant 3T1D-Based Cache Architectures"
  Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei and David M. Brooks
  The 40th International Symposium on Microarchitecture (MICRO-40), December 2007 (Chicago, Illinois)

• "Process Variation Tolerant Register Files Based on Dynamic Memories"
  Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei and David M. Brooks
  ASGI'07,Workshop on Architectural Support for Gigascale Integration (In conjunctoin with ISCA 2007), June 2007 (San Diego, California)

Journals

• " Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives"
  Y Sazeides, A Bramnik, R Gabor, R Canal
  IEEE Transactions on Emerging Topics in Computing v.10 n.2 pp. 524-536; April-June 2022

• " Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives"
  R. Canal, C. Hernández, R. Tornero, A. Cilardo, G. Massari, F. Reghenzani, W. Fornaciari, M. Zapater, D. Atienza,A. Oleksiak, W. Piatek, J. Abella
  ACM Computing Surveys, v. 53, n. 5, a. 95; September 2020

• " The RECIPE Approach to Challenges in Deeply Heterogeneous High Performance Systems"
  G. Agosta, W. Fornaciari, D. Atienza, R. Canal, A. Cilardo, J. Flich, C. Hernandez, M. Kulczewski, G. Massari, R. Tornero, M. Zapater,
  Microprocessors and Microsystems, v. 77; September 2020 [ArXiv]

• " On the Use of Probabilistic Worst-Case Execution Time Estimation for Parallel Applications in High Performance Systems "
  M. Fusi, F. Mazzocchetti, A. Farres, L. Kosmidis, R. Canal, F. J. Cazorla, J. Abella
  Mathematics 2020, v.8, n.3; pp. 314-335; March 2020

• "SyRA: Early System Reliability Analysis for Cross-layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems"
  A. Vallero, A. Savino, A. Chatzidimitriou, M. Kaliorakis, M. Kooli, M. Riera, M. Anglada, G. Di Natale, A. Bosio, R. Canal, A. González, D. Gizopoulos, R. Mariani and S. Di Carlo 
  IEEE Transactions on Computers  v. 68, n. 5, pp. 765-783; May 2019

• "Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design "
  M. Anglada, R. Canal, J.L. Aragón, A. González
  IEEE Transactions on Sustainable Computing  v. X, n. Y, Accepted December 2018 (Available as Early Access)

• "Optimization of FinFET-Based Gain Cells for Low Power Sub-VT Embedded DRAMs"
  E. Amat, A. Calomarde, R. Canal, A. Rubio
  Journal of Low Power Electronics v. 14, n. 2, June 2018

• "Review on suitable eDRAM configurations for next nano-metric electronics era"
  E. Amat, A. Calomarde, R. Canal, A. Rubio
  International Journal of the Society of Materials Engineering for Resources, v.23, n.1, pp.22-29, March 2018

• "Statistical Analysis and Comparison of 2T and 3T1D e-DRAM Minimum Energy Operation"
  M.Rana, R. Canal, E. Amat, A. Rubio 
  IEEE Transactions on Device and Materials Reliability v. 17, n.1, pp. 42-51, March 2017

• "Feasibility of the embedded DRAM cells implementation with FinFET devices"
  E. Amat, A. Colomarde, F. Moll, R. Canal, A. Rubio 
  IEEE Transactions on Computers v.65 n. 4, pp. 1068-1074, April 2016

• "Variability Influence on FinFET-based On-chip Memory Data Paths"
  E. Amat, A. Colomarde, F. Moll, R. Canal, A. Rubio
  Journal of Low Power Electronics v. 11, n. 2, June 2015

• "Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22nm"
  E. Amat, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio 
  Microelectronics Journal v. 45, n. 10,  pp. 1342–1347, October 2014

• "Suitability of the FinFET 3T1D cell beyond 10nm"
  E. Amat, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio 
  IEEE Transactions on Nanotechnology v.13, n.5, pp.926-932, September 2014

• "Impact of FinFET and III-V/Ge technology on logic and memory cell behavior"
  E. Amat, A. Calomarde, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio
  IEEE Transactions on Device and Materials Reliability v.14, n. 1, pp.  344 - 350, March 2014

• "Impact of FinFET technology introduction in the 3T1D-DRAM memory cell"
  E. Amat, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio
  IEEE Transactions on Device and Materials Reliability v.13, n. 1, pp. 287-292, March 2013

• "Variability mitigation mechanisms in scaled 3T1D DRAM memories to 22nm and beyond"
  E. Amat, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio
  IEEE Transactions on Device and Materials Reliability v.13, n.1, pp. 103-109, March 2013

• "Comparison of SRAM Cells for 10nm SOI FinFETs Under Process and Environmental Variations"
  Z.  Jakšić, R. Canal
  IEEE Transactions on Electron Devices, v.60 n.1 pp.49-55, January 2013

• "Impact of Positive Bias Temperature Instability (PBTI) on 3T1D-DRAM Cells"
  N. Aymerich, S. Ganapathy, A.Rubio, R. Canal, A. Gonzalez
  Integration, the VLSI Journal, Elsevier. December 2011.

• "TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies"
  R. Canal, A. Rubio, A. Asenov, A. Brown, M. Miranda, P. Zuber, A. Gonzalez and X. Vera
  Proceedings of the 2nd European Future Technologies Conference and Exhibition 2011 (FET 11),  Procedia Computer Science, Volume 7, pp. 148-149. 2011

• "Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability"
  Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei and David M. Brooks
  IEEE Micro Micro's Top Picks from Computer Architecture Conferences, v.28 n.1 pp.60-68 Jan/Feb 2008

Posters/Workshops w/o proceedings

• "Soft-Error Vulnerability Evolution:A 4D study (bulk/SOI, planar/FinFET)"
  M. Riera, R. Canal, A. Gonzalez, J. Abella, M. Anglada, M. Torrents
  1st International Workshop on Reliability and Aging in Forthcoming Electronic Systems (in conjunction with ETS'15), May 2015

• "Cache Design Under Spatio-Temporal Variability"
  S. Ganapathy, R. Canal, A. Gonzalez, A. Rubio
  Intel 2010 European Research and Innovation Conference, Braunschweig (Germany), September 2010

• "DRAM-based On-Chip Cache Architectures to Combat Process Variations"
  Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei and David M. Brooks
  Intel 2008 European Research and Innovation Conference, Leixlip (Ireland), September 2008

Barcelona, July 2022