Eduard Ayguade home page (Technical University of Catalonia

PhD Thesis

Jordi Torres i Viñals. Extracció Automática de Paral.lelisme en Bucles Seqüencials Numèrics amb Recurrencies. Advisor. Universitat Politècnica de Catalunya. 1993. (UPC Best Thesis Award, 1993).
Montse Peiron Guàrdia. Optimització del Rendiment del Sistema de Memòria en Multiprocessadors Vectorials. Co-advisor with Prof. Mateo Valero. Universitat Politècnica de Catalunya. 1995.
Josep Llosa Espuny. Reducing the Impact of Register Pressure on Software Pipelining. Co-advisor with Prof. Mateo Valero. Universitat Politècnica de Catalunya. 1996. (UPC Best Thesis Award).
Jordi Garcia Alminyana. Distribución Automática de Datos en MPP. Advisor. Universitat Politècnica de Catalunya. 1997.
Javier Zalamea León. Organization and Compiler Management of Register Files. Co-advisor with Josep Llosa. Universitat Politècnica de Catalunya. 2002.
Daniel Ortega Fernandez. Memory Instruction Bypassing. Co-advisor with Mateo Valero. Universitat Politècnica de Catalunya. 2003.
Marc Gonzalez Tallada. Multilevel Parallelism Exploitation in Shared-memory Multiprocessor Systems. Co-advisor with Xavier Martorell. Universitat Politècnica de Catalunya. 2003.
Jordi Guitart. Performance Improvement of Multithreaded Java Applications Execution on Multiprocessor Systems. Co-advisor with Jordi Torres. Universitat Politècnica de Catalunya. 2005
David Carrera Perez. Adaptive Execution Environments for Application Servers. Co-advisor with Jordi Torres. Universitat Politècnica de Catalunya. 2008
Vicenç Beltran Querol. Improving Web Server Efficiency on Commodity Hardware. Co-advisor with Jordi Torres. Universitat Politècnica de Catalunya. 2008
Alejandro Duran Gonzalez. Self-tuned Parallel Runtimes: a Case of Study for OpenMP. Co-advisor with Julita Corbalan. Universitat Politècnica de Catalunya. 2008

Conferences and Journals

Compiler and runtime support for multicore programming models

David Ródenas, Xavier Martorell, Eduard Ayguade, Jesús Labarta, George Almasi, Calin Cascaval, José Castaños, Jose Moreira. Optimizing NANOS OpenMP for the IBM Cyclops Multithreaded Architecture. 19th International Parallel and Distributed Processing Symposium, April 2005.
David Ródenas, Xavier Martorell, Eduard Ayguadé, Jesus Labarta, George Almási, Calin Cascaval, José Castaños, and José Moreira. Multilevel Parallelism using OpenMP on a Massive Multithreaded Architecture. Journal of Embedded Computing, Special issue: Issues in embedded single-chip multicore architectures, Vol 2(2), pp.141-155. April 2006.
Tim Harris, Adrian Cristal, Osman S. Unsal, Eduard Ayguade, Simon P. Jones, Fabrizio Gagliardi, Burton Smith and Mateo Valero. Transactional Memory: An Overview. IEEE Micro. Hot Tutorials Special Issue. Vol. 27, Issue 3. pp. 8-29. May/June 2007.
Miloš Milovanović, Roger Ferrer, Osman S. Unsal, Adrian Cristal, Xavier Martorell, Eduard Ayguadé, Jesús Labarta and Mateo Valero. Transactioonal Memory and OpenMP. International Workshop on OpenMP (IWOMP 2007). Beijing, China. June 2007. In Lecture Notes in Computer Science, vol. 4935, pp. 37-53. ISBN 0302-9743. Springer-Verlag, 2008.
Paul Carpenter, David Rodenas, Xavier Martorell, Alex Ramirez, Eduard Ayguade. An streaming machine description and programming models. SAMOS VII: International Symposium on Systems, Architectures, Modeling and Simulation, Samos, Greece. Embedded Computer Systems: Architectures, Modeling, and Simulation, LNCS vol. 4599/2007, pp. 107-116. Springer. July 2007.
Ferad Zyulkyarov, Osman S Unsal, Adrian Cristal, Milos Milovanovic, Eduard Ayguade and Mateo Valero. Memory Management for Transaction Processing Core in Heterogeneous Chip-Multiprocessors. OSHMA 2007: Workshop on Operating System support for Heterogeneous Multicore Architectures. In conjunction with Parallel Architectures and Compilation Techniques (PACT-2007). Brasov, Rumania. September 2007.
Miloš Milovanović, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrian Cristal, Eduard Ayguadé and Mateo Valero. Multithreaded Software Transactional Memory and OpenMP. MEDEA 2007: MEmory performance Workshop: DEaling with Applications, systems and architecture. In conjunction with Parallel Architectures and Compilation Techniques (PACT-2007). Brasov, Rumania. September 2007.
Jairo Balart, Marc Gonzalez, Xavier Martorell, Eduard Ayguade, Zehra Sura, Tong Chen, Tao Zhang, Kevin O’Brien and Kathryn O’Brien. A Novel Asynchronous Software Cache Implementation for the Cell-BE Processor. LCPC 2007: 20th International Workshop on Languages and Compilers for Parallel Computing. Urbana (IL), USA. October 2007. In Lecture Notes in Computer Science, vol. 5234/2008, pp. 125-140. ISBN 0302-9743 . Springer-Verlag, 2008.
Milos Milovanovic, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero. Nebelung: Execution Environment for Transactional OpenMP. International Journal of Parallel Programming vol. 36 no. 3. pp. 326-346. ISSN: 0885-7458. Springer, 2008.
Nikola Vujic, Marc Gonzalez, Xavier Martorell and Eduard Ayguadé. Automatic Pre-Fetch and Modulo Scheduling Transformations for the Cell BE Architecture. 21st Annual Workshop on Languages and Compilers for Parallel Computing (LCPC). University of Alberta. July 31- August 2, 2008. In Lecture Notes in Computer Sciences, vol. 5335/2008, Springer-Verlag, 2008.
Ferad Zyulkyarov, Sanja Cvijic, Osman Unsal, Adrian Cristal, Eduard Ayguadé, Tim Harris and Mateo Valero. WormBench - A Configurable Workload for Evaluating Transactional Memory Systems. MEDEA -- MEmory performance: DEaling with Applications, systems and architecture (workshop held in conjunction with PACT-2008). Toronto, Canada. October 25-29, 2008.
Marc Gonzalez, Nikola Vujic, Xavier Martorell, Eduard Ayguadé, Alexandre E. Eichenberger, Tong Chen, Zehra Sura, Tao Zhang, Kevin O’Brien, and Kathryn O’Brien. Hybrid Access-Specific Software Cache Techniques for the Cell BE Architecture. The 17th International Conference on Parallel Architectures and Compilation Techniques (PACT). Toronto, Canada. October 25-29, 2008.
Roger Ferrer, Marc Gonzalez, Federico Silla, Xavier Martorell, Eduard Ayguadé. Evaluation of Memory Performance on the Cell BE with the SARC Programming Model. MEDEA -- MEmory performance: DEaling with Applications, systems and architecture (workshop held in conjunction with PACT-2008). Toronto, Canada. October 25-29, 2008.

Compiler and runtime support for shared-memory programming models (OpenMP)

X. Martorell, J. Labarta, J.I. Navarro and E. Ayguadé, A Library Implementation of the Nano-Threads Programming Model. Euro-Par’96, Lyon (France). Lecture Notes in Computer Science, Springer-Verlag. Vol. 1124, pp. 644-649. August 1996.
X. Martorell, J. Labarta, J.I. Navarro and E. Ayguadé, Analysis of Several Scheduling Algorithms under the Nano-Threads Programming Model. 11th IEEE International Parallel Processing Symposium IPPS’97, Geneve (Suiza). Lecture Notes in Computer Science, Springer-Verlag. Vol. 1124, pp. 644-649. April 1997.
E. Ayguadé , X. Martorell, J. Labarta, M. Gonzalez and J.I. Navarro , Exploiting Parallelism Through Directives on the Nano-Threads Programming Model. 10th Workshop on Programming Languages and Compilers for Parallel Computing, Minneapolis (USA), August 1997.
X. Martorell, E. Ayguadé, N. Navarro, J. Corbalan, M. Gonzalez and J. Labarta, Thread Fork/join Techniques for Multi-level Parallelism Exploitation in NUMA Multiprocessors. 13th International Conference on Supercomputing (ICS’99), Rhodes (Greece). June 1999.
X. Martorell, E. Ayguadé, J. Labarta and N. Navarro, Improving the Performance of Multiprogrammed Workloads in Origin2000 Systems. 5th European Cray/SGI MPP Workshop, Bologna (Italy). September 1999.
E. Ayguadé, X. Martorell, J. Labarta, M. Gonzalez and N. Navarro, Exploiting Multiple Levels of Parallelism in OpenMP: A Case Study. 29th Annual International Conference on Parallel Processing (ICPP’99), Aizu (Japan). September 1999.
E. Ayguadé, M. Gonzalez, J. Labarta, X. Martorell, N. Navarro, J. Oliver, NanosCompiler: A Research Infrastructure for OpenMP Extensions. 1st European Workshop on OpenMP (EWOMP’99), Lund (Sweden). September/October 1999.
M. Gonzalez, X. Martorell, J. Oliver, E. Ayguadé and J. Labarta, Code Generation and Run-time Support for Multi-level Parallelism Exploitation. 8th International Workshop on Compilers for Parallel Computing (CPC’00), Aussois (France). January 2000.
M. Gonzalez, X. Martorell, J. Oliver, A. Serra, E. Ayguadé, J. Labarta and N. Navarro, Applying Interposition Techniques for Performance Analysis of OpenMP Parallel Applications. IEEE 2000 International Parallel and Distributed Processing Symposium (IPDPS’2000), Cancun (Mexico). May 2000.
J. Oliver, E. Ayguadé and N. Navarro, Towards an Efficient Exploitation of Loop-level Parallelism in Java. ACM Java Grande 2000 Conference, San Francisco CA (USA). June 2-4, 2000.
J. Oliver, E. Ayguadé, N. Navarro, J. Guitart, J. Torres and J. Labarta. Strategies for the Efficient Exploitation of Loop-level Parallelism in Java. Concurrency and Computation: Practice and Experience (Java Grande 2000 Special Issue). Vol. 13(8-9). pp. 663-680. July 2001.
M. Gonzalez, J. Oliver, X. Martorell, E. Ayguadé, J. Labarta and N. Navarro, OpenMP Extensions for Thread Groups and Their Run-time Support. 13th International Workshop on Languages and Compilers for Parallel Computing (LCPC’2000), New York (USA). August, 2000. Also in Languages and Compilers for Parallel Computing. Lecture Notes in Computer Science LNCS 2017. S.P. Midkiff, J.E. Moreira, M. Gupta, S. Chatterjee, J. Ferrante, J. Prins, W. Pugh, C.-W. Tseng (Eds.). pp. 324-338. 2001.
M. Gonzalez, J. Oliver, X. Martorell, E. Ayguadé, J. Labarta and N. Navarro,
Precedence Relations in the OpenMP Programming Model. 2nd European Workshop on OpenMP (EWOMP’00), Edimburgh (UK), September 2000.
J. Labarta, E. Ayguadé, J. Oliver and D. Henty, New OpenMP Directives for Irregular Data Access Loops. 2nd European Workshop on OpenMP (EWOMP’00), Edimburgh (UK), September 2000.
M. Gonzalez, E. Ayguadé, X. Martorell, J. Labarta, N. Navarro and J. Oliver, NanosCompiler: Supporting Flexible Multilevel Parallelism in OpenMP. Concurrency: Practice and Experience. Special issue on OpenMP. vol. 12, no. 11. November 2000.
M. Gonzalez, E. Ayguadé, X. Martorell and J. Labarta. Defining and Supporting Pipelined Executions in OpenMP. 2nd International Workshop on OpenMP Applications and Tools. July 2001. OpenMP Shared Memory Parallel Programming, R. Eigenmann and M. Voss (Eds.), Lecture Notes on Computer Science LNCS 2104, pp. 155-169, Springer. 2001.
D. Nikolopoulos, E. Artiaga, E. Ayguadé and J. Labarta. Exploiting Memory Affinity in OpenMP through Schedule Reuse. 3rd European Workshop on OpenMP (EWOMP’01) in conjunction with the 10th International Conference on Parallel Architectures and Compilation Techniques (PACT’01). Barcelona (Spain) September 2001. Also in ACM SIGARCH Computer Architecture News. Vol. 29, no. 5, pp. 49-55, ACM Press, December 2001.
E. Ayguadé, M. Brorsson, H. Brunst, H.-C. Hoppe, S. Karlsson, X. Martorell, W.E. Nagel, F. Schlimbach, G. Utrera and M. Winkler. OpenMP Performance Analysis Approach in the INTONE Project. 3rd European Workshop on OpenMP (EWOMP’01) in conjunction with the 10th International Conference on Parallel Architectures and Compilation Techniques (PACT’01). Barcelona (Spain) September 2001.
H. Jin, G. Jost, J. Yan, E. Ayguadé, M. Gonzalez and X. Martorell. Automatic Multilevel Parallelization Using OpenMP. 3rd European Workshop on OpenMP (EWOMP’01) in conjunction with the 10th International Conference on Parallel Architectures and Compilation Techniques (PACT’01). Barcelona (Spain) September 2001. Also in Scientific Programming. Vol. 11, no. 2. pp. 177-190. June 2003.
M. Gonzalez, E. Ayguadé, X. Martorell and J. Labarta. Complex Pipelined Executions in OpenMP Parallel Applications. International Conference on Parallel Processing (ICPP’01). September 2001.
D. Nikolopoulos, E. Ayguadé and C. D. Polychronopoulos. Scaling Irregular Parallel Codes with Minimal Programming Effort. REF. REVISTA/LIBRO: ACM/IEEE Supercomputing’2001: High Performance Networking and Computing Conference (SC’2001). Denver, Colorado (USA). November 2001.
J. Labarta, E. Ayguade, J. Oliver and D. Henty. New OpenMP Directives for Irregular Data Access Loops. Scientific Programming. Vol. 9, no. 2-3. IOS Press, March 2002.
M. González, E. Ayguadé, X. Martorell, J. Labarta and P-V. Luong. Dual-Level Parallelism Exploitation with OpenMP in Coastal Ocean Circulation Modeling. 2nd Workshop on OpenMP: Experiences and Implementations (WOMPEI’02 part of ISHPC-02). Kyoto (Japan), May 2002. Published in Lecture Notes in Computer Science LNCS 2327, Springer. May 2002.
D. S. Nikolopoulos, E. Ayguadé and C. D. Polychronopoulos. Runtime vs. Manual Data Distribution for Architecture-agnostic Shared-memory Programming Models. International Journal of Parallel Programming, vol. 30, no. 4. Plenum Publishing Corporation. August 2002.
E. Artiaga, N. Navarro, E. Ayguade, J. Labarta. Dynamic Loop Schedulers and Memory Behavior. Fourth European Workshop on OpenMP (EWOMP 2002). Rome, Italy, September 2002.
D. S. Nikolopoulos, E. Artiaga, E. Ayguadé and J. Labarta. Scaling Non-Regular Shared-Memory Codes by Reusing Custom Loop Schedules. Scientific Programming. Scientific Programming. Vol. 11, no. 2. pp. 143-159. June 2003.
Eduard Ayguade, Bob Blainey, Alejandro Duran, Jesus Labarta, Francisco Martinez, Xavier Martorell and Raul Silvera. Is the SCHEDULE Clause Really Necessary in OpenMP? International Workshop on OpenMP Applications and Tools. June 2003. M.J. Voss (Editor), Lecture Notes on Computer Science, vol. LNCS 2716, pp. 69–83. Springer-Verlag. 2003.
George Almasi, Eduard Ayguade, Calin Cascaval, Jose Castanos, Jesus Labarta, Fracisco Martinez, Xavier Martorell and Jose Moreira. Evaluation of OpenMP for the Cyclops Mulithreaded Architecture. International Workshop on OpenMP Applications and Tools. June 2003. M.J. Voss (Editor), Lecture Notes on Computer Science, vol. LNCS 2716, pp. 147–159. Springer-Verlag. 2003.
Marc Gonzalez, Eduard Ayguadé, Xavier Martorell and Jesús Labarta. Exploiting Pipelined Executions in OpenMP. 32nd Annual International Conference on Parallel Processing (ICPP’03). Kaohsiung, Taiwan. October 2003.
E. Ayguadé, M. Gonzalez, X. Martorell and G. Jost. Employing Nested OpenMP for the Parallelization of Multi-Zone Computational Fluid Dynamics Applications . International Parallel and Distributed Processing Symposium (IPDPS’2004). Santa Fe, NM (USA). April 2004.
J. Balart, A. Duran, M. Gonzàlez, X. Martorell, E. Ayguadé and J. Labarta. Skeleton driven transformations for an OpenMP compiler. 11th Workshop Compilers for Parallel Computers (CPC'04). Pp. 123-134. Seeon, Germany. July 2004.
J. Balart, A. Duran, M. Gonzàlez, X. Martorell, E. Ayguadé and J. Labarta. Nanos Mercurium: A Research Compiler for OpenMP. European Workshop on OpenMP (EWOMP'04). Pp. 103-109. Stockholm, Sweden. October 2004.
Jairo Balart, Alejandro Duran, Marc Gonzalez, Xavier Martorell, Eduard Ayguade and Jesus Labarta. Experiences Parallelizing a Web Server with OpenMP. 1st International Workshop on OpenMP (IWOMP-2005), Eugene, Oregon USA. June 1-4, 2005
A. Duran, M. Gonzalez, J. Corbalan, X. Martorell, E. Ayguade, J. Labarta and R. Silvera. Automatic Thread Distribution For Nested Parallelism In OpenMP. 19th ACM International Conference on Supercomputing (ICS’05), Cambridge, MA, USA, June 20 - 22, 2005
Marc Gonzalez, Eduard Ayguadé, Xavier Martorell and Jesús Labarta. Nested Parallelism and Pipelining in OpenMP. High-Performance Computing: Paradigm and Infrastructure, Chapter 6. T. Yang and M. Guo Eds. John Wiley & Sons, Inc. July 2005. ISBN: 0-471-65471-X
X. Martorell, M. Gonzalez, A. Duran, J. Balart., R. Ferrer, E. Ayguade and J. Labarta. Techniques supporting threadprivate in OpenMP. 11th International Workshop on High-Level Parallel Programming Models and Supportive Environments HIPS 2006 (in conjuntion with 20th International Parallel and Distributed Processing Symposium IPDPS 2006), April 2006.
Alejandro Duran, Roger Ferrer, Juan Jose Costa, Marc González, Xavier Martorell, Eduard Ayguadé and Jesús Labarta. A proposal for error handling in OpenMP. 2nd International Workshop on OpenmP (IWOMP 2006), Reïms (France), June 2006. Best papers also published International Journal of Parallel Programming, Vol. 35, No. 4, pp. 393-416. August 2007.
Eduard Ayguade, Nawal Copty, Alejandro Duran, Jay Hoeflinger, Yuan Lin, Federico Massaioli, Ernesto Su, Priya Unnikrishnan, Guansong Zhang. A Proposal for Task Parallelism in OpenMP. International Workshop on OpenMP (IWOMP 2007). Beijing, China. June 2007. In Lecture Notes in Computer Science, vol. 4935, pp. 1-12. Springer-Verlag, 2008.
Eduard Ayguadé, Alejandro Duran, Jay Hoeflinger, Federico Massaioli and Xavier Teruel. An Experimental Evaluation of the New OpenMP Tasking Model. LCPC 2007: 20th International Workshop on Languages and Compilers for Parallel Computing. Urbana (IL), USA. October 2007. In Lecture Notes in Computer Science. Vol. 5234/2008, pp. 63-77. ISBN 0302-9743, Springer-Verlag, 2008.
Alejandro Duran, Julita Corbalán and Eduard Ayguadé. Evaluation of OpenMP Task scheduling strategies. International Workshop on OpenMP (IWOMP-2008). Purdue University, West Lafayette (IN, USA). May 12-14, 2008. In Lecture Notes in Computer Sciences, vol. 5004/2008, pp. 100-110. ISBN 978-3-540-79560-5, Springer-Verlag, 2008.
Alejandro Duran, Josep M. Perez, Eduard Ayguadé, Rosa M. Badia and Jesus Labarta. Extending the OpenMP Tasking Model to Allow Dependent Tasks. International Workshop on OpenMP (IWOMP-2008). Purdue University, West Lafayette (IN, USA). May 12-14, 2008. In Lecture Notes in Computer Sciences, vol. 5004/2008, pp. 111-122. ISBN 978-3-540-79560-5, Springer-Verlag, 2008.
Xavier Teruel, Priya Unnikrishnan, Xavier Martorell, Eduard Ayguadé, Raul Silvera, Guansong Zhang and Ettore Tiotto. OpenMP Tasks in IBM XL compilers. CASCON-2008, Toronto (Canada). October 27-30, 2008.

Compiler and runtime support for distributed-memory architectures (HPF and SDSM)

E. Ayguadé, J. Labarta, J. Garcia, M. Gironès and M. Valero, A Study of Data Sets and Affinity in the Perfect ClubTM. 4th International Workshop on Compilers for Parallel Computers, Delft (The Netherlands). pp. 5-16. December 1993.
E. Ayguadé, J. Garcia, M. Girones, J. Labarta, J. Torres and M. Valero, Detecting and Using Affinity in an Automatic Data Distribution Tool. 7th Workshop on Languages and Compilers for Parallel Computing, Ithaca (NY), August 1994. Languages and Compilers for Parallel Computing, (Springer-Verlag), K. Pingali et al. (Eds.), Lecture Notes in Computer Science, Springer-Verlag. Vol. 892. pp. 61-75. 1995.
J. Garcia, E. Ayguadé and J. Labarta, A Novel Approach Towards Automatic Data Distribution. 2nd Workshop on Automatic Data Layout and Performance Prediction, CRPC Technical Report CRPC-TR95548, Houston-TX (USA), April 1995.
E. Ayguadé, J. Garcia, M. Girones, M.L. Grande and J. Labarta, Data Redistribution in an Automatic Data Distribution Tool. 8th Workshop on Languages and Compilers for Parallel Computing, San Jose (CA), August 1995. Languages and Compilers for Parallel Computing, (Springer-Verlag), Huang et al. (Eds.) Lecture Notes in Computer Science, Springer-Verlag. Vol. 1033, pp. 271-287. 1996.
J. Garcia, E. Ayguadé and J. Labarta, A Novel Approach Towards Automatic Static Data Distribution. IEEE/ACM Supercomputing’95, San Diego-CA (USA). December 1995.
E. Ayguadé, J. Labarta, J. Garcia, M. Gironès and M. Valero, Analyzing Reference Patterns in Automatic Data Distribution Tools. International Journal of Parallel Programming. Vol. 23, no. 6, pp. 515-535. December 1995.
J. Garcia, E. Ayguadé and J. Labarta, Using a 0-1 Integer Programming Model for Automatic Static Data Distribution. Parallel Processing Letters, World Scientific Publishing Co. Vol. 6, no. 1, pp. 159-171. 1996.
E. Ayguadé, J. Garcia, M. L. Grande, and J. Labarta, Data Distribution and Loop Parallelization for Shared-memory Multiprocessors. Ninth Workshop on Languages and Compilers for Parallel Computing, San Jose (CA). Languages and Compilers for Parallel Computing, (Springer-Verlag), D. Sehr et al. (Eds.) Lecture Notes in Computer Science, Springer-Verlag. Vol. 1239, pp. 41-55. August 1996.
J. Garcia, E. Ayguadé, and J. Labarta, A Framework for Automatic Dynamic Data Mapping. Eighth IEEE Symposium on Parallel and Distributed Processing SPDP’96, New Orleans (Louisiana). pp. 92-99. October 1996.
J. Garcia, E. Ayguadé and J. Labarta, Dynamic Data Distribution with Control Flow Analysis. IEEE/ACM Supercomputing’96, Pittsburgh (PA). November 1996.
E. Ayguadé, J. Garcia, M. L. Grande and J. Labarta, Using Pipelined Computations in Parallelizing Compilers. XVI International Conference of the Chilean Computer Sciency Society, Valdivia (Chile). pp. 165-174. November 1996.
J. Garcia, E. Ayguadé, and J. Labarta, Two-dimensional Data Redistribution with Constant Topology. 3rd Workshop on Automatic Data Layout and Performance Prediction. UPC/CEPBA Research Report 97-02. January 1997.
E. Ayguadé, J. Garcia, M. Girones, M. L. Grande, and J. Labarta, DDT: A Research Tool for Automatic Data Distribution in HPF. Scientific Programming, Special Issue on Implementations of HPF. Vol. 6, no. 1, pp. 73-94. Spring 1997.
R. Perrott, E. Ayguadé, J. Garcia, and J. Torres, High Performance Fortran Implementations: A Survey. Scientific Programming. Vol. 6, no. 3, pp. 243-248, 1998.
E. Ayguadé, J. Garcia and U. Kremer, Tools and Techniques for Automatic Data Layout: A Case Study. Parallel Computing, Special Issue on Languages and Compilers for Parallel Computing. North Holland. Vol. 24, no. 3. 1998.
M. Kandermir, P. Banerjee, A. Choudhary, J. Ramanujam and E. Ayguadé, An Integer Linear Programming Approach for Optimizing Cache Locality. 13th International Conference on Supercomputing (ICS’99), Rhodes (Greece). June 1999.
D.S. Nikolopoulos, T.S. Papatheodorou, C.D. Polychronopoulos, J. Labarta and E. Ayguadé, A Case for User-level Dynamic Page Migration. 14th ACM International Conference on Supercomputing (ICS’00), Santa Fe, New Mexico (USA). May 2000.
D.S. Nikolopoulos, T.S. Papatheodorou, C.D. Polychronopoulos, J. Labarta and E. Ayguadé, UPMLib: A Runtime System for Tuning the Memory Performance of OpenMP Programs on Scalable Shared-memory Multiprocessors. 5th ACM Workshop on Languages, Compilers, and Run-time Systems for Scalable Computers (LCR2000), Lecture Notes in Computer Science, vol. 1915. Sandhya Dwarkadas (Ed.). Rochester NY (USA). May 2000.
D.S. Nikolopoulos, T.S. Papatheodorou, C.D. Polychronopoulos, J. Labarta and E. Ayguadé, User-level Dynamic Page Migration for Multiprogrammed Shared-memory Multiprocessors. 30th Annual International Conference on Parallel Processing (ICPP’00), Vancouver (Canada). August 2000.
D.S. Nikolopoulos, T.S. Papatheodorou, C.D. Polychronopoulos, J. Labarta and E. Ayguadé, Leveraging Transparent Data Distribution in OpenMP via User-level Dynamic Page Migration.
3rd International Symposium on High-Performance Computing, Workshop on OpenMP: Experiences and Implementations, Tokyo (Japan). October 2000.
D.S. Nikolopoulos, T.S. Papatheodorou, C.D. Polychronopoulos, J. Labarta and E. Ayguadé, Is Data Distribution Necessary in OpenMP?. IEEE/ACM Supercomputing’2000: High Performance Computing and Networking Conference, Dallas-TX (USA). November 2000.
J. Garcia, E. Ayguadé and J. Labarta. A Framework for Integrating Data Alignment, Distribution and Redistribution in Distributed Memory Multiprocessors. IEEE Transactions on Parallel and Distributed Systems. Vol. 12, no. 4. April 2001.
D.S. Nikolopoulos, E. Ayguadé, T.S. Papatheodorou, C.D. Polychronopoulos and J. Labarta
The Trade-off between Implicit and Explicit Data Distribution in Shared-memory Programming Paradigms. 15th International Conference on Supercomputing (ICS’01). pp. 23-37. ACM Press. Sorrento (Italy). June 2001.
D.S. Nikolopoulos, T.S. Papatheodorou, C.D. Polychronopoulos, J. Labarta and E. Ayguadé. A Transparent Runtime Data Distribution Engine for OpenMP. Scientific Programming, IOS Press. Vol. 8(3), pp. 143-162. July 2001.
D. Nikolopoulos and E. Ayguadé. A Study of Implicit Data Distribution Methods for OpenMP Using the SPEC Benchmarks. 2nd International Workshop on OpenMP Applications and Tools. July 2001. OpenMP Shared Memory Parallel Programming, R. Eigenmann and M. Voss (Eds.), Lecture Notes on Computer Science LNCS 2104, pp. 115-129, Springer. 2001.
M. Kandermir, P. Banerjee, A. Choudhary, J. Ramanujam and E. Ayguadé. Static and Dynamic Locality Optimizations Using Integer Linear Programming. IEEE Transactions on Parallel and Distributed Systems. Vol. 12, no. 9, pp. 922-941. September 2001.
D. Nikolopoulos, T. S. Papatheodorou, C. D. Polychronopoulos, J. Labarta and E. Ayguadé. Scheduler-activated Dynamic Page Migration for Multiprogrammed DSM Multiprocessors.
Journal of Parallel and Distributed Computing. Vol. 62, no. 6. Academic Press. June 2002.
J.J. Costa, T. Cortes, X. Martorell, E. Ayguade and J. Labarta. Running OpenMP applications efficiently on an everything-shared SDSM. International Parallel and Distributed Processing Symposium (IPDPS’2004). Santa Fe, NM (USA). April 2004. (IPDPS’04 Best Paper Award)
Jairo Balart, Marc Gonzàlez, Xavier Martorell, Eduard Ayguadé and Jesús Labarta. Runtime Address Space Computation for SDSM Systems. The 19th Int. Workshop on Languages and Compilers for Parallel Computing (LCPC 2006), New Orleans, Louisiana, November 2006. Volume LNCS 4382/2007, pp. 330 – 344, 2007.

Architecture and resource management for application servers

J. Guitart, J. Torres, E. Ayguadé, J. Oliver and J. Labarta, Java Instrumentation Suite: Accurate Analysis of Java Threaded Applications. 2nd Workshop on Java for High Performance Computing (part of the 14th ACM International Conference on Supercomputing ICS’00), Santa Fe, New Mexico (USA). May 7, 2000.
J. Guitart, J. Torres and E. Ayguadé. Efficient Execution of Parallel Java Applications. 3rd Workshop on Java for High-Performance Computing, in conjunction with the 15th International Conference on Supercomputing (ICS’01). Sorrento (Italy). June 2001.
J. Guitart, J. Torres, E. Ayguadé and M. Bull. Performance Analysis of Parallel Java Applications on Shared-memory Systems. International Conference on Parallel Processing (ICPP’01). September 2001.
D. Carrera, J. Guitart, J. Torres, E. Ayguadé and J. Labarta. Complete Instrumentation Requirements for Performance Analysis of Web based Technologies. 2003 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). Austin, Texas (USA), March 2003.
J. Guitart, X. Martorell, J. Torres and E. Ayguadé. Application/Kernel Cooperation Towards the Efficient Execution of Shared-memory Parallel Java Codes. 2003 International Parallel and Distributed Processing Symposium (IPDPS-2003). Nice, France. April 2003.
V. Beltran, D. Carrera, J. Torres and E. Ayguadé. Evaluating the Scalability of Java Event-Driven Web Servers. The 2004 International Conference on Parallel Processing (ICPP’04). Montreal (Canada). August 2004.
David Carrera, David García, Jordi Torres, Eduard Ayguadé and Jesús Labarta. WAS Control Center: An Autonomic Performance-Triggered Tracing Environment for WebSphere. 13th Euromicro Conference on Parallel, Distributed and Network-based Processing (PDP'05), Lugano, Switzerland, February 2005.
Jordi Guitart, David Carrera, Jordi Torres, Eduard Ayguadé and Jesús Labarta. Tuning Dynamic Web Applications using Fine-Grain Analysis. 13th Euromicro Conference on Parallel, Distributed and Network-based Processing (PDP'05), Lugano, Switzerland, February 2005.
David Carrera, Jordi Guitart, Vicenç Beltran, Jordi Torres and Eduard Ayguadé. Performance Impact of the Grid Middleware. Engineering the Grid: Status and Perspective, Nova Science Publisher, To appear 2005.
Jordi Guitart, Vicenç Beltran, David Carrera, Jordi Torres, Eduard Ayguade. Characterizing Secure Dynamic Web Applications Scalability. 19th International Parallel and Distributed Processing Symposium, April 2005
J. Guitart, V. Beltran, D. Carrera, J. Torres, E. Ayguadé. Session-Based Adaptative Overload Control for Secure Dynamic Web Application. The 2005 International Conference on Parallel Processing (ICPP-05), Oslo, Norway June 14-17, 2005
D. Carrera, V. Beltran, J. Torres and E. Ayguadé. A Hybrid Web Server Architecture for e-Commerce Applications. 11th International Conference on Parallel and Distributed Systems (ICPADS 2005), July 20 - 22, 2005, Fukuoka, Japan
V. Beltran, D. Carrera, J. Torres and E. Ayguadé. A Hybrid Web Server Architecture for Secure e-Business Web Applications. The 2005 International Conference on High Performance Computing and Communications (HPCC 05), September 21-24, 2005, Naples, Italy
David Carrera, Jordi Guitart, Vicenç Beltran, Jordi Torres and Eduard Ayguadé. Performance Impact of the Grid Middleware. Engineering the GRID – Status and Persperctives, B. DiMartino, J. Dongarra, A. Hoisie, L. Yang and H. Zima Eds. American Scientific Publishers. November 2005. ISBN: 1-58883-038-1
V. Beltran, D. Carrera, J. Torres and E. Ayguadé. A Hybrid Web Server Architecture for e-Commerce Applications. ICPADS-2005 Special Issue on High Performance Computing in Parallel and Distributed Systems, IJHPCN Journal, InderScience Publishers, to appear.
Jordi Guitart, David Carrera, Vicenç Beltran, Jordi Torres, Eduard Ayguade. Designing an Overload Control Strategy for Secure e-Commerce Applications. Computer Networks Journal. Elsevier. Vol. 51, Issue 15. October, 2007
Vicenç Beltran, Jordi Torres and Eduard Ayguadé. Improving Disk Bandwidth-Bound Applications Through Main Memory Compression. MEDEA 2007: MEmory performance Workshop: DEaling with Applications, systems and architecture. In conjunction with Parallel Architectures and Compilation Techniques (PACT-2007). Brasov, Rumania. September 2007.
David Carrera, Malgorzata Steinder, Ian Whalley, Jordi Torres and Eduard Ayguadé. Utility-based Placement of Dynamic Web Applications with Fairness Goals. NOMS 2008, IEEE/IFIP Network Operations and Management Symposium. Salvador de Bahia, Brazil. April 7-11, 2008.
Vicenç Beltran, Jordi Torres and Eduard Ayguadé. Understanding Tuning Complexity in Multithreaded and Hybrid Web Servers. 22nd IEEE International Parallel and Distributed Processing Symposium. Miami, Florida USA. April 14-18, 2008.
Jordi Guitart, David Carrera, Vicenc Beltran, Jordi Torres and Eduard Ayguadé. Dynamic CPU Provisioning for Self-Managed Secure Web Applications in SMP Hosting Platforms. Computer Networks Journal. Elsevier. Vol 52/7. pp 1390-1409, ISSN:1389-1286, May 2008.
Jordi Torres, David Carrera, Vicenç Beltran, Nicolás Poggi, Kevin Hogan, Josep Ll. Berral, Ricard Gavaldà, Eduard Ayguadé, Toni Moreno and Jordi Guitart. Tailoring resources: the energy efficient consolidation strategy goes beyond virtualization. The 5th IEEE International Conference on Autonomic Computing (ICAC-2008). Chicago (IL, USA), pp. 197-198, June 2-6, 2008.
David Carrera, Malgorzata Steinder, Ian Whalley, Jordi Torres and Eduard Ayguadé. Managing SLAs of Heterogeneous Workloads using Dynamic Application Placement. HPDC-17, ACM/IEEE International Symposium on High-Performance Distributed Computing. Boston June 23-27. ISBN 978-1-59593-997-5. pp. 217-218, 2008.
V. Beltran, D. Carrera, J. Torres and E. Ayguadé. A Hybrid Web Server Architecture for e-Commerce Applications. ICPADS-2005 Special Issue on High Performance Computing in Parallel and Distributed Systems, IJHPCN Journal, InderScience Publishers, ISSN: 1740-0562. 2008.
Vicenç Beltran, Jordi Torres and Eduard Ayguadé. Improving Web Server Performance Through Main Memory Compression. The 14th IEEE International Conference on Parallel and Distributed Systems (ICPADS'08). Melbourne (Australia). December 8-10, 2008.
David Carrera, Malgorzata Steinder, Ian Whalley, Jordi Torres and Eduard Ayguadé. Enabling Resource Sharing between Transactional and Batch Workloads Using Dynamic Application Placement. 9th ACM/IFIP/USENIX International Middleware Conference (Middleware 2008). Leuven (Belgium). December 1-5, 2008.

Architecture and compilation techniques for VLIW processors

J. Llosa, M. Valero, J. Fortes and E. Ayguadé, Using Sacks to Organize Registers in VLIW Machines. CONPAR 94 - VAPP VI, Linz (Austria). Lecture Notes in Computer Science, Springer-Verlag. Vol. 854, pp. 628-639. September 1994.
J. Llosa, M. Valero, E. Ayguadé, and J. Labarta, Register Requirements of Software Pipelined Loops and its Effects on Performance. 2nd International Workshop on Massive Parallelism, Capri-Italy, pp. 173-189. October 1994.
C. Barrado, J. Labarta and E. Ayguadé, An Efficient Scheduling for DOACROSS Loops. Parallel and Distributed Computing and Systems, Washington DC. pp. 303-307. October 1994.
J. Llosa, M. Valero and E. Ayguadé, Non-consistent Dual Register Files to Reduce Register Pressure. IEEE Int. Symp. on High-Performance Computer Architecture HPCA-1, Raleigh (USA), pp. 22-31. January 1995.
C. Barrado, J. Labarta, E. Ayguadé and M. Valero, Automatic Generation of Loop Schedulings for VLIW. 3rd Parallel Architectures and Compilation Techniques PACT’95, Cyprus (Greece). pp. 306-309. June 1995.
C. Barrado, J. Labarta, E. Ayguadé, and M. Valero, Generating a Periodic Pattern for VLIW. 5th International Workshop on Compilers for Parallel Computers, Malaga. pp. 485-502. June 1995.
J. Llosa, M. Valero, and, E. Ayguadé, Bidirectional Scheduling to Minimize Register Requirements. 5th International Workshop on Compilers for Parallel Computers, Malaga. pp. 534-554. June 1995.
J. Llosa, M. Valero, E. Ayguadé and A. Gonzalez, Hypernode Reduction Modulo Scheduling. MICRO-28, 28th International Symposium on Microarchitecture, Ann Arbor-MI (USA). pp. 350-360. December 1995.
J. Llosa, A. Gonzalez, E. Ayguadé and M. Valero, Swing Modulo Scheduling: A Lifetime-Sensitive Approach. 4th Parallel Architectures and Compilation Techniques PACT’96, Boston (MA). pp. 80-86. October 1996.
J. Llosa, M. Valero, and E. Ayguadé, Heuristics for Register-constrained Software Pipelining. 29th International Symposium on Microarchitecture (MICRO-29), Paris (France). pp. 250-261. December 1996.
D. Lopez, M. Valero, J. Llosa and E. Ayguadé, Increasing Memory Bandwidth with Wide Busses: Compiler, Hardware and Performance Trade-offs. 11th International Conference on Supercomputing (ICS’97), Vienna (Austria). pp. 12-19. July 1997.
J. Llosa, E. Ayguadé and M. Valero, Quantitative Evaluation of Register Pressure on Software Pipelined Loops. International Journal of Parallel Programming. Vol. 26, no. 2, 1998.
J. Llosa, M. Valero, E. Ayguadé and A. González, Modulo Scheduling with Reduced Register Pressure. IEEE Transactions on Computers. Vol. 47, no. 6. pp. 625-638. June 1998.
D. Lopez, J. Llosa, M. Valero and E. Ayguadé, Resource Widening vs. Replication: Limits and Performance-cost Trade-off. 12nd International Conference on Supercomputing (ICS’98), Melbourne (Australia). pp. 441-448. July 1998.
D. Lopez, J. Llosa, M. Valero and E. Ayguadé, Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures. 31st Annual International Symposium on Microarchitecture (Micro-31), Dallas, TX (USA). November 1998.
D. Lopez, J. Llosa, E. Ayguadé and M. Valero, Impact on Performance of Fused Multiply-Add Functional Units in Aggressive VLIW Architectures. 29th Annual International Conference on Parallel Processing (ICPP’99), Aizu (Japan). September 1999.
J. Zalamea, J. Llosa, E. Ayguadé and M. Valero, Improved Spill Code Generation for Software Pipelined Loops. ACM SIGPLAN 2000 Conference on Programming Language Design and Implementation (PLDI’00), Vancouber B.C. (Canada). June 2000.
J. Zalamea, J. Llosa, E. Ayguadé and M. Valero, Two-level Hierarchical Register File Organization for VLIW Processors. 33rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-33), Monterrey CA (USA). December, 2000.
J. Llosa, E. Ayguadé, A. González, M. Valero and J. Eckhardt, Lifetime-sensitive Modulo Scheduling in a Production Environment. IEEE Transactions on Computers. Vol. 50, no. 3, pp. 234-249. March 2001.
J. Zalamea, J. Llosa, E. Ayguadé and M. Valero. Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. The International Workshop on Advanced Compiler Technology for High Performance and Embedded Systems. July 2001. Also published in International Journal of Parallel Programming, vol. 32, no. 6, pp. 447-474. December 2004.
J. Zalamea, J. Llosa, E. Ayguadé and M. Valero. MIRS: Modulo Scheduling with Integrated Register Spilling. 14th Workshop on Languages and Compilers for Parallel Computing. Cumberland Falls, Kentucky (USA). August 2001.
D. Lopez, J. Llosa, M. Valero and E. Ayguadé. Cost-conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. IEEE Transactions on Computers. Vol. 50, no.10, pp.1033-1051. October 2001.
J. Zalamea, J. Llosa, E. Ayguadé and M. Valero. Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures. 34th Annual International Symposium on Microarchitecture. Austin, Texas (USA). pp. 160-169. December 2001.
J. Zalamea, J. Llosa, E. Ayguadé and M. Valero. Hierarchical Clustered Register File Organization for VLIW Processors. 2003 International Parallel and Distributed Processing Symposium (IPDPS-2003). Nice, France. April 2003.
M. Pericas, E. Ayguadé, J. Zalamea, J. Llosa and M. Valero. Power and Performace Evaluation of Widened and Clustered VLIW Cores. SAMOS III: International Workshop on Systems, Architectures, Modeling and Simulation. Samos, Greece. July 21-23, 2003.
M. Pericas, E. Ayguadé, J. Zalamea, J. Llosa and M. Valero. Power–Performance Trade–Offs in Wide and Clustered VLIW Cores for Numerical Codes. The fifth International Symposium on High Performance Computing (ISHPC-V), Tokyo, Japan. October 20-22, 2003. Lecture Notes in Computer Science (LNCS), vol. 2858, Springer-Verlag.
J. Zalamea, J. Llosa, E. Ayguadé and M. Valero. Register-constrained Modulo Scheduling. IEEE Transactions on Parallel and Distributed Systems, vol. 15, no. 5, May 2004.
Miquel Pericas, Eduard Ayguadé, Javier Zalamea, Josep Llosa and M. Valero. Power–Efficient VLIW Design Using Clustering and Widening. International Journal of Embedded Systems (IJES). Special Issue on Systems and Architectures for Embedded Processing: Design Methods and Tools. Inderscience Publishers. Vol. 3, no. 3, pp. 141-149. October 2008.

Superscalar and Multithreaded Processors

I. Martel, D. Ortega, E. Ayguadé and M. Valero, Increasing Effective IPC by Exploiting Distant Parallelism. 13th International Conference on Supercomputing (ICS’99), Rhodes (Greece). June 1999.
D. Ortega, I. Martel, V. Krishnan, E. Ayguadé and M. Valero, A Characterization of SPECint Programs in Simultaneous Multi-threading Architectures. International Conference on Parallel Architectures and Compilation Techniques (PACT’99), Newport Beach-CA (USA). October 1999.
R. A.L Gonçalves, E. Ayguadé, M. Valero and P. Navaux, A Simulator for SMT Architectures: Evaluating Instruction Cache Topologies. 12th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD’2000), Sao Paulo (Brasil). October 2000.
D. Ortega, M. Valero and E. Ayguadé. A Novel Mechanism that Boost Software Prefetching. 15th International Conference on Supercomputing (ICS’01). Sorrento (Italy). June 2001.
R. A.L Gonçalves, E. Ayguadé, M. Valero and P. Navaux. Performance Evaluation of Decoding and Dispatching Stages in Simultaneous Multithreaded Architectures. 13th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD’2001), Pirenópolis (Brasil). 10-12 September 2001.
D. Ortega, E. Ayguadé, J-L. Baer and M. Valero. A Novel Mechanism that Boosts Software Prefetching. 11 th Parallel Architectures and Compilation Techniques (PACT’02). Virginia, USA, September 2002.
Daniel Ortega, Mateo Valero and Eduard Ayguadé. Dynamic Memory Instruction Bypasssing. 17th Annual ACM International Conference on Supercomputing, San Francisco (CA). June 2003. Also to be published in the International Journal on Parallel Programming. Special issue with papers from ICS’2003. Vol. 32, no. 3, June 2004.
Tomer Morad, Uri Weiser, Avinoam Kolodny, Mateo Valero and Eduard Ayguadé. Performance, Power Efficiency and Scalability of Asymmetric Chip Multiprocessors. IEEE Computer Architecture Letters. Vol. 5, Issue 1, pp. 14-17. January 2006.

Vector Architectures

M. Valero, T. Lang, J.M. Llabería, M. Peiron, J.J. Navarro and E. Ayguadé, Conflict-Free Strides for Vectors in Matched Memories. Parallel Processing Letters, World Scientific Publishing Co. Vol.1, no. 2, pp. 95-102. 1991.
M. Valero, T. Lang, J.M. Llabería, M. Peiron, E. Ayguadé and J.J. Navarro, Increasing the Number of Strides for Conflict-Free Vector Access. ISCA’92, International Symposium on Computer Architecture, Gold Coast (Australia). ACM Computer Architecture News. Vol. 20, no. 2, pp. 372-381. May 1992.
M. Valero, T. Lang and E. Ayguadé, Conflict-Free Access of Vectors with Power-of-Two Strides. 6th ACM International Conference on Supercomputing ICS, Washington. pp. 149-156. July 1992.
M. Peiron, M. Valero, E. Ayguadé and T. Lang, Conflict-Free Access to Streams in Multiprocessor Systems. 19th EUROMICRO Conference, Barcelona. Microprocessing and Microprogramming. Vol. 38, no. 1-5, pp. 119-130. September 1993.
M. Peiron, M. Valero, E. Ayguadé and T. Lang, Synchronized Access to Streams in Vector Multiprocessors. IEEE TC on Computer Architecture Newsletter. Fall issue, pp. 37-41. 1993.
M. Valero, M. Peiron and E. Ayguadé, Access to Streams in Multiprocessor Systems. EUROMICRO Workshop on Parallel and Distributed Processing, Gran Canaria. pp. 310-316. January 1993.
M. Valero, M. Peiron and E. Ayguadé, Access to Vectors in Multi-module Memories. 2nd EUROMICRO Workshop on Parallel and Distributed Processing, Malaga. pp. 228-236. January 1994.
M. Peiron M. Valero, and E. Ayguadé, Synchronized Access to Streams in SIMD Vector Multiprocessors. 8th ACM International Conference on Supercomputing ICS, Manchester (UK). pp. 23-32. July 1994.
M. Valero, M. Peiron and E. Ayguadé, Memory Access Synchronization in Vector Multiprocessors. CONPAR 94 - VAPP VI, Linz (Austria). Lecture Notes in Computer Science, Springer-Verlag. Vol. 854, pp. 414-425. September 1994.
M. Valero, E. Ayguadé, and M. Peiron, Network Synchronization and Out-of-order Access to Vectors. Parallel Processing Letters, World Scientific Publishing Co. Vol.4, no. 4, pp. 405-415. 1994.
R. Espasa, M. Valero, D. Padua, M. Jiménez and E. Ayguadé, Quantitative Analysis of Vector Code. 3rd EUROMICRO Workshop on Parallel and Distributed Processing, San Remo (Italia). pp. 452-461. January 1995.
M. Valero, T. Lang, M. Peiron and E. Ayguadé, Conflict-Free Access for Streams in Multi-module Memories. IEEE Transactions on Computers. Vol. 44, no. 5, pp. 634-646. May 1995.
M. Peiron, M. Valero, E. Ayguadé and T. Lang, Vector Multiprocessors with Arbitrated Memory Access. 22nd ISCA Int. Symposium on Computer Architecture, S. Margherita Ligure (Italy). ACM Computer Architecture News. Vol. 23, no. 2, pp. 243-252. June 1995.

Loop transformations and parallelization

J. Labarta and E. Ayguadé, GTS: Extracting Full Parallelism Out of DO Loops. PARLE’89, Parallel Architectures and Languages Europe. Lectures in Computer Science, Springer-Verlag. No. 366, pp. 43-54. June 1989.
E. Ayguadé and J. Labarta, J. Torres and P. Borensztejn, GTS: Parallelization and Vectorization of Tight Recurrences. Supercomputing’89, Reno-Nevada. pp. 531-539. November 1989.
E. Ayguadé, J. Labarta, J. Torres, J.M. Llabería and M. Valero, Parallelism Evaluation and Partitioning of Nested Loops for Shared-Memory Multiprocessors. Third Workshop on Languages and Compilers for Parallel Computing, Irvine (CA), August 1990. Also in Advances in Programming Languages and Compilers for Parallel Computing, A. Nicolau et al. (Eds.), chapter 11, Pitman/The MIT Press, 1991.
E. Ayguadé, J. Labarta, J. Torres, J.M. Llabería and M. Valero, Nested-Loop Partitioning for Shared-Memory Multiprocessor Systems. 2nd International Workshop on Compilers for Parallel Computers, Paris (France). pp. 378-385. December 1990.
J. Torres, E. Ayguadé, J. Labarta, J.M. Llaberia, and M. Valero, Automatic Data-Mapping for Distributed-Memory Multiprocessors Systems. 9th International Symposium on Applied Informatics, Innsbruck, Austria. pp. 347-350. February 1991. Also in International Journal of Mini and Microcomputers. Vol. 15, no. 3, pp. 109-115. 1993.
J. Torres, E. Ayguadé, J. Labarta, J.M. Llaberia and M. Valero, On Automatic Loop Data-Mapping for Distributed-Memory Multiprocessors. 2nd European Distributed Memory Computing Conference, Munich-Germany. Lecture Notes in Computer Science, Springer-Verlag . Vol. 487, pp. 173-182. April 1991.
J. Labarta, E. Ayguadé, J. Torres, J.M. Llabería and M. Valero, Balanced Loop Partitioning Using GTS. Fourth Workshop on Languages and Compilers for Parallel Computing, Santa Clara (CA), August 1991. Also in Languages and Compilers for Parallel Computing, U. Banerjee et al. (Eds.), chapter 19, Lecture Notes in Computer Science, Springer-Verlag. Vol. 589. 1992.
J. Torres, E. Ayguadé, J. Labarta and J. Llosa, Parallel Execution of Loops with Conditional Statements. 11th International Conference Applied Informatics, Annecy, France. pp. 37-40. May 1993.
E. Ayguadé and J. Torres, Partitioning the Statement per Iteration Space Using Non-singular Matrices. 7th ACM International Conference on Supercomputing ICS, Tokyo, Japan. pp. 407-415. July 1993.
J. Torres, E. Ayguadé, J. Labarta and M. Valero, Align and Distribute based Linear Loop Transformations. Sixth Workshop on Languages and Compilers for Parallel Computing, Portland (OR), August 1993. Languages and Compilers for Parallel Computing, U. Banerjee et al. (Eds.), Lecture Notes in Computer Science, Springer-Verlag . Vol. 768, pp. 321-339. 1994.
J. Torres, E. Ayguadé, J. Labarta, and M. Valero, Revisiting Framework of Linear Loop Transformations. 5th International Workshop on Compilers for Parallel Computers, Malaga. pp. 187-199. June 1995.
E. Ayguadé, P. Knijnenburg, and J. Torres, Multi-transformations: Definition and Usefulness. XV Int. Conference of the Chilean Computer Science Society, Arica-Chile. pp. 37-47. October 1995.
J. Torres, E. Ayguadé, J. Labarta, and M. Valero, Loop Parallelization: Revisiting Framework of Linear Loop Transformations. 4th EUROMICRO Workshop on Parallel and Distributed Processing, Braga (Portugal). pp. 420-427. January 1996.